Solid state digital-to-analog converter

ABSTRACT

A digital-to-analog converter comprising an IC switch module providing four switch transistors and associated switch-control buffering circuitry. The emitter areas of the switch transistors are binarily weighted to provide equal current densities. The IC substrate also is formed with a fifth transistor to serve as a reference transistor for adjusting the supply voltage as necessary to maintain constant current through the switch transistors. To construct a digital-to-analog converter having a high bit resolution, a number of such &#34;quad&#34; switch modules may be combined, for example in a printed circuit card assembly including a thin-film resistor module providing binarily-weighted resistors on a glass substrate to set the current levels through the switch transistors.

This invention relates to digital-to-analog converters. Moreparticularly, this invention relates to such converters based onsolid-state electronics.

Digital-to-analog (D-A) converters have been required for a wide varietyof purposes, such as transforming the digital outputs of a high-speedcomputer to corresponding analog voltages. D-A converters also are usedin analog-to-digital converters. A wide variety of D-A converter designshave been proposed, and a number have been sold commercially. Aparticularly successful design is disclosed in co-pending applicationSer. No. 809,700 filed by the present inventor on Mar. 24, 1969.Badd.,now U.S. Pat. No. 3,685,045.Baddend.. Reference to that earlierapplication is hereby made for details of certain design features whichare also incorporated in the embodiment of the present invention to bedescribed below, and the priority date of that earlier application isherein asserted for such common subject matter.

With the development of integrated-circuit (IC) technology, efforts havebeen made to produce D-A converters in IC form, seeking the benefits ofimproved reliability, small size, low power consumption, and lowproduction costs. However, prior IC converter designs have not suitablyadapted IC technology to the special requirements of D-A converters, andhave not satisfactorily exploited the real potential of such technology.It is therefore one goal of the present invention to provide D-Aconverter designs which achieve superior characteristics from a uniqueadaptation of integrated-circuit concepts and processing.

In a preferred embodiment of the invention to be described hereinbelowin detail, there is provided a D-A converter comprising a number ofseparate interconnected modules. The basic module of this converter isan IC switch unit having a single monolithic substrate in which has beendiffused a number of switching transistors, together with associatedcontrol and logic circuitry for selectively activating the switches inaccordance with a digital input signal. One or more such switch modulesare .[..[.assmelbed.]..]. .Badd.assembled .Baddend.on a printed circuitboard together with a resistor module having a set of precision meteringresistors which fix the level of current through the switchingtransistors in a binary weighting pattern.

The preferred switch module arrangement provides four switchingtransistors, and thus has been called a "quad-switch." D-A convertershaving resolutions of 4, 8, 12 or 16 bits can readily be provided, in aflexible manner, simply by using one, two, three or four identical"quad-switch" modules. Current-dividers of 16:1 attenuation ratio (or10:1 for binary coded decimal) are used to reduce the current levelsfrom the second, third or fourth switch modules to obtain the correctcurrent contribution for each bit of the digital input.

The conductive areas of the switching transistors of each quad-switchmodule are binarily weighted in the ratio of 8:4:2:1. Thus eachconductive area is directly proportional to the current carried by theassociated transistor, so that the current density is the same for allswitching transistors. This provides important benefits, includingsuperior tracking and lower offset differences between switches. Eachswitch module substrate also is formed with an additional referencetransistor which controls the supply voltage for all the switchingtransistors so as to effect nearly perfect compensation for thevariables which can cause errors in the analog output signal.

Accordingly, it is an object of this invention to provide a superior D-Aconverter design based on IC technology. A further object of thisinvention is to provide a D-A converter having markedly improvedperformance characteristics. Still another object of this invention isto provide a D-A converter which can be manufactured economically, andwhich can flexibly be applied to meet diverse requirements. Otherobjects, aspects, and advantages of the invention will in part bepointed out in, and in part apparent from, the following descriptionconsidered together with the accompanying drawings, in which:

FIG. 1 shows schematically the circuit arrangement of a quad-switchmodule and its associated resistance network;

FIG. 2 is a schematic plan view of the portion of the IC chip(substrate) carrying the switching transistors of the quad-switch moduleof FIG. 1;

FIG. 3 is a cross-section taken along line 3--3 of FIG. 2, showing thelayers defining the different transistor segments;

FIG. 4 shows schematically how three identical quad-switch modules arecombined with a resistor module to form a 12-bit D-A converter;

FIG. 5 is a schematic diagram showing a compensation circuit forstabilizing the converter output with changes in ambient temperatureand/or other variables;

FIG. 6 is a schematic diagram illustrating a modified form ofcompensation circuit;

FIG. 7 is a wiring diagram of a 12-bit D-A converter; and

FIG. 8 shows the physical arrangement of the principal components makingup the D-A converter illustrated in FIG. 7.

Referring now to FIG. 1, a .[..[.quad-swtich.]..]. .Badd.quad-switch.Baddend.module 10 is schematically illustrated as a single monolithicsubstrate 12 having diffused therein four .[..[.seprate.]..]..Badd.separate .Baddend.switching transistors generally indicated at 14,16, 18 and 20. Each transistor is represented symbolically as a numberof parallel-connected sub-transistors, with the numbers ofsub-transistors differing in accordance with a binary weighting pattern,i.e., in a ratio of 8:4:2:1.

The switching transistors are arranged as current sources, and theoutputs of all of the transistors are connected together to a commonline 22. The transistors are selectively activated by respective switchcontrol and logic circuits comprising buffer transistors 24, 26, 28, 30controlled through corresponding diodes 34, 36, 38, 40 in accordancewith the respective bits of a digital input signal. A detaileddescription of such a switch control circuit is set forth in theabovementioned co-pending application Ser. No. 809,700.

The first transistor 14 provides a current output level representing themost-significant bit (MSB) of the digital input signal, the nexttransistor 16 provides half as much current representing thesecond-most-significant-bit, and so forth. The current level in eachcase is determined by a respective current-weighting metering resistor44, 46, 48, 50 forming part of a separate resistor module 52. The ohmicresistances of these resistors may, for example, be 10K, 20K, 40K and80K, respectively, to produce switch currents of 1 ma., 0.5 ma., 0.25ma., and 0.125 ma.

Referring also to FIGS. 2 and 3, all of the transistors 14-20 havecollector, base, and emitter segments diffused in the substrate 12. Theconductive areas of these transistors are binarily weighted tocorrespond with the current flowing through the transistor.Specifically, the total areas of the respective emitters 54, 56, 58, 60are in direct proportion to the currents to be carried by thecorresponding transistors.

In the preferred embodiment, the emitter areas are so proportioned byproviding for each transistor a predetermined number of equal-areaemitters 54A, 54B, . . . 56A, 56B, . . . etc., with the number ofemitters for each transistor being in accordance with a binary weightingpattern. Thus, the right-hand transistor 20 includes a single emitter 60of preselected area, the next transistor 18 includes two emitters 58A,58B of that preselected area, and so forth. The size of the base segment64, 66, 68, 70 of each transistor is roughly proportioned to thesurrounding emitter area, and a single common collector segment 72 isprovided for all transistors of the switch module.

By proportioning the emitter areas of the switching transistors 14-20 tothe level of current to be carried, the current density is made uniformthroughout the conducting regions of all transistors. This results inessentially equal base-to-emitter voltages (V_(BE)) for all of theswitching transistors. Initial offset between switches, as well asoffset drift between switches, are minimized by this arrangement, so asto provide improved accuracy. Because all transistors are diffused on asingle common substrate, the transistor characteristics (particularly"Beta") will be effectively matched for all switches, further minimizingerrors in the output due to changes in variables such as temperature.

The resistor module 52 is assembled together with the switch module 10by interconnecting means, preferably a single printed circuit board. Theresistor module comprises a non-conductive substrate 74 (glass or thelike) on which is deposited by known techniques (e.g., sputtering) athin film of a metallic substance such as nichrome, arranged to form aset of resistors having the required ohmic resistance. Resistors of thistype have very low temperature coefficients, so that there will be onlysmall changes in current with changes in temperature. By having all ofthe resistors on a single substrate, and formed of the same material,any changes in resistance will be proportionately the same for allresistors, thereby assuring uniform performance characteristics for theindividual switches.

FIG. 4 shows schematically a 12-bit D-A converter composed of threeidentical quad-switch modules 10A, 10B, 10C assembled with a binaryresistor module 52 as described above. The resistor network includesthree identical sets 80A, 80B, 80C of four current-weighting resisotrs44, 46, 48, 50. The resistors of each set are connected to therespective transistors 14, 16, 18, 20 of a corresponding quad-switchmodule as described above. The resistor module also includescurrent-dividing networks 82, 84 which attenuate the currents from thesecond and third quad-switch modules by factors of 16:1 and 256:1.

One important advantage of the module construction described above isthat the range of required resistance values is relatively low. Forexample, in the preferred quad-switch module, the resistance rangerequired is only 8:1, a range well suited for commercial processing. Incomparison, a conventional straight 12-bit converter would require aresistance range of 2048:1, e.g., a 10K resistor for the MSB and a 20megohm resistor for the LSB.

It is difficult to make resistors of such widely different values as 10Kand 20 megohm from the same resistance alloy. On the other hand, ifdifferent materials are used for the high and low value resistors, theywill have different temperature coefficients, and hence will introducetracking errors with changes in operating temperature. Tracking errorslead to degraded linearity and loss of monotonicity. Loss of linearityresults in unequal incremental steps. Loss of monotonicity means that,at some points, the output current will decrease in response to anincreased digital number.

These problems and difficulties are avoided or substantially minimizedby the module construction described hereinabove, wherein the range ofresistance values required for each switch module is relatively small,and the resistors are formed by thin film deposition on a singlesubstrate. Moreover, the modular concept permits the current through theLSB transistor switch to be large relative to the transistor leakage.For example, in the preferred four-transistor "quad-switch" package, thesmallest switch current is 0.125 ma., well above the transistor leakagelevel. In comparison, the LSB current in a straight 12-bit converter maybe as low as 500 nanoamps, which begins to approach the transistorleakage value and hence may well be subject to switching error.

Another advantage of the modular concept described hereinabove is thatit simplifies production testing. A quad-switch, for example, need betested only for 16 different codes. Thus a total of only 48 code testsneed be made for the three quads used to make up a 12-bit converter. Incomparison, a conventional straight converter may require testing by1,000 or so codes, leading to higher manufacturing cost.

The modular concept provides another benefit in manufacturing, becauseit divides the IC processing into smaller but identical units. In the ICprocess, the "yield" (i.e., the proportion of acceptable units) isgenerally proportional to the size of a unit, whereas the cost isgenerally proportional to the square of the size. By sub-dividing thecomplete device into a set of identical smaller units, the overallmanufacturing operation is made more effective.

The module arrangement described herein lends itself well to standardcommercial packaging configurations, such as the DIP pack (14 or 16 pin)or the so-called flat-pack. Thus the converter is well adapted forflexible application to many different types of electronic apparatusrequirements.

The provision of exactly four switching transistors in each module is anespecially advantageous feature. This number of switches affords anapparently optimum balance between the need to minimize the range ofcurrent-weighting resistance values and the need to reduce the number ofseparate components which must be assembled into a complete unit. Italso represents a practical number of switches which can be providedwith equal current densities in an IC configuration. Also of importanceis the fact that quad-switches can readily be assembled to provideeither a straight binary conversion, or a binary-coded-decimal (BCD)conversion, simply by selecting the appropriate current-dividingattenuation networks between the separate quad units.

Further refinements in performance can be obtained by using acompensation circuit as shown in FIG. 5. In this arrangement, aquad-switch module 10, like that in FIG. 1, is provided with anadditional transistor 100 diffused in the substrate 12 (see also FIG.2). This additional transistor serves as a reference for controlling thebase supply voltage for the four switching transistors.

The reference transistor 100 is identical to the LSB transistor 20,having a single emitter and a base like that of the LSB transistor. Theresistor module 52 is provided with an additioanl 80K current-meteringresistor 102 for the reference transistor. The base of the referencetransistor is connected to the common base rail 104 for the switchingtransistors.

The current flowing into the reference transistor 100 is fixed atexactly 0.125 ma. by a regulated current source comprising a Zener diode106, a current-setting reference resistor 108, and an operationalamplifier 110 the output of which drives the base of the referencetransistor (and thereby drives the bases of all of the switchingtransistors due to the common base rail 104). The reference resistor 108is trimmed to the precise value to produce 0.125 ma. into the collectorof the reference resistor. Since the LSB switching transistor isidentical to the reference transistor (same size emitter and base), andboth are connected to identical resistors 50, 102 of the resistor module52, the current into the LSB transistor also must be 0.125 ma., and thecurrent densities must be equal. And since the other switchingtransistors are, in effect, exact multiples (binarily weighted) of theLSB transistor, the currents through those other transistors similarlywill be exact binary multiples of the LSB current.

In more detail, the reference current established by zener diode 106 andreference resistor 108 is summed with the collector current of thereference transistor 100. The operational amplifier 110 adjusts thevoltage of the common base line 104 to make the two currents equal. Withthe reference current thus properly established, all other currents willbe in the correct proportion to one another, since the base-to-emitterdrops (V_(BE)) of all of the IC transistors will be equal.

Any changes in the parameters of the switching-transistor circuitry willbe compensated for by the feedback action of the amplifier 110, whichwill tend to hold constant the current into the collector of referencetransistor 100, and thereby (in open loop mode) hold constant the actualoutput currents of the switching transistors. Any change in a circuitparameter which tends to alter the collector currents of the switchingtransistors 14-20 will similarly tend to alter the reference transistorcollector current from equality with the originally establishedreference current. Such a tendency of the reference transistor collectorcurrent to change will be sensed at the input to amplifier 110, and itsoutput will alter the base voltage of the reference transistor (and thebases of all of the switching transistors) so as to maintain theoriginal current levels.

It should be noted that the reference transistor collector currentcorresponds identically to the currents of the switching transistorswhich must be held constant. That is, the output of the D-A converteris, basically, the collector currents of the activated switchingtransistors. Thus, by holding constant the reference transistorcollector current, and thereby holding constant the switching transistorcollector currents, the output of the D-A converter will be heldconstant even in the face of changes in such parameters as base current,collector leakage current, or base-to-emitter-voltage.

The temperature performance of the unit is enhanced by the fact that theadditional metering resistor 102 is part of the resistor module 52.Tracking between resistance values of such thin film resistors is ±1part-per-million per °C., so that any temperature-induced change inresistance of the current-weighting resistors 44-50 will be accompaniedby a corresponding change in the resistance of resistor 102. Theresulting tendency of the current through reference transistor 100 tochange will be sensed by the operational amplifier 110, and its outputwill change correspondingly to adjust the base voltages so as to holdthe currents constant.

Advantageously, the resistor module 52 also contains the power supplyreference resistor 108 and the feedback resistor 114 of an outputoperational amplifier 116. If there is a change in resistance of thereference resistor 108, there will be a corresponding change in thecollector currents of all of the transistors of the quad-switch, butthis will be compensated for by a change in the resistance of thefeedback resistor 114, so as to maintain the final output substantiallyconstant.

FIG. 6 shows another compensation arrangement for the quad-switch module10. Here the common base line 120 for the switching transistors is tiedto a fixed voltage (e.g., -3 volts), and the output of the referenceamplifier 110 controls the voltage of the common line 122 to which allof the resistors are connected. In general, this compensationarrangement works on much the same basic principles as that of FIG. 5,in that the output of the reference amplifier is automaticallycontrolled by sensing the differential between a reference currentthrough resistor 108 and the collector current of the referencetransistor 100. The amplifier in effect adjusts the voltage differentialapplied to the transistor base-to-emitter circuits so as to hold thecollector currents constant.

The arrangement of FIG. 6 includes biasing circuitry used in a typicalIC quad-switch module 10. This circuitry includes clamping diodes124-130 to keep the buffer transistors 24-30 from saturating when thosePNP devices are diverting the currents from the associated switchingtransistors. The circuit also incorporates transistors 132, 134, 136 forsetting the base voltage of the buffer transistors.

FIG. 7 is a wiring diagram showing details of a complete D-A converterusing three quad-switch modules 10A, 10B, 10C and a resistor module 52interconnected by conductive elements of a printed circuit board. FIG. 8illustrates the physical arrangement of the several components. Inputconnections to the converter are made through contacts 140 on one edgeof the circuit board. The parallel digital input signal is directedthrough corresponding leads to three 4-bit registers 142, 144, 146 wherethe digital bits are strobed into respective storage stages forapplication to the input diodes of the switch control circuitry in eachquad-switch.

The resistor module 52 contains all of the current-weighting resistors,the 16:1 current-dividing networks 82, 84, the power supply referenceresistor 108, and the output feedback resistor 114. The referenceamplifier 110 controls the common resistor line 122, as in the FIG. 6arrangement discussed above. Although all quad-switch modules containreference transistors 100, only one is neede for controlling the commonresistor line. The reference transistor in the first module 10A is usedfor this purpose. The printed circuit board carries the referenceamplifier 110 and the output operational amplifier 116, and performs theusual function of furnishing interconnections between the differentcomponents, as shown in the diagram.

Although preferred embodiments of the invention have been describedhereinabove in detail, it is desired to emphasize that such details havebeen disclosed for the purpose of illustrating the nature of theinvention, and should not be considered as necessarily limiting of theinvention which can be expressed in many modified forms to meetparticular requirements.

I claim:
 1. An integrated-circuit digital-to-analog convertercomprising: resistor..]..]..Baddend. .Badd..[..[.4. A converter as inclaim 1, wherein said substrate is formed with four switchingtransistors the emitters of which have areas in the ratios of1:2:4:8..]..]..Baddend. .Badd..[..[.5. Apparatus as in claim 1, whereinsaid substrate has said plurality of transistors diffused therein toserve as separate current sources corresponding to respective bits of adigital input signal;each of said transistors comprising an emitter, abase and a collector; the areas of the respective emitters for saidtransistors differing in accordance with a binary weightingpattern..]..]..Baddend. .Badd..[..[.6. Apparatus as in claim 5, whereineach of said transistors has a number of separate equal-size emittersections, with the number of sections in each case being in accordancewith said binary weighting pattern..]..]..Baddend. .Badd..[..[.7.Apparatus as in claim 5, wherein the size of the base segment for eachtransistor is at least approximately proportional to the area of thecorresponding emitter..]..]..Baddend. .Badd..[..[.8. Apparatus as inclaim 7, wherein said substrate is formed with a single collectorsegment common to all of said transistors..]..]..Baddend. .Iadd..[..[.9.An integrated-circuit digital-to-analog converter comprising:a pluralityof transistors on a single monolithic substrate; an output line; switchcontrol means operable by a digital input for selectively activating anyof said transistors to pass the current thereof through said outputline; circuit means for said transistors to set different levels ofcurrent through each transistor according to a predetermined weightingpattern such that the sum of the currents produced in said output lineby the selected transistors represents an analog output corresponding tosaid digital input; each of said transistors being formed to present insaid substrate a respective conductive area proportional to theparticular current level assigned thereto in accordance with saidweighting pattern to provide uniform current density in the activatedtransistors..]..]..Iaddend. .Iadd..[..[.10. Apparatus as in claim 9,wherein the emitter area of each of said transistors is proportional tothe particular current level assigned thereto..]..]..Iaddend.
 11. Anintegrated-circuit digital-to-analog converter comprising: a .Badd.first.Baddend.plurality of transistors on a single monolithic substrate eachadapted to conduct current; an output line; .Badd.first .Baddend.meansoperable by a first part of a digital input signal for developing insaid output line a flow of current representing the summation of thecurrents of any of said .Badd.first .Baddend.transistors selected inaccordance with .Badd.said first part of .Baddend.said digital inputsignal; circuit means for said .Badd.first .Baddend.transistors to setdifferent levels of current therethrough according to a predeterminedweighting pattern such that the sum of the currents produced in saidoutput line by the transistors represents .Iadd..[..[.an.]..]..Iaddend..Badd.a first .Baddend.analog output signal corresponding to said.Badd.first part of said .Baddend.digital input signal; each of said.Badd.first .Baddend.transistors being formed to present in saidsubstrate a respective conductive area proportional to the particularcurrent level assigned thereto in accordance with said weighting patternto provide uniform current density in said transistors. .Badd.; a secondplurality of transistors on a substrate each adapted to conduct current;said second plurality of transistors being matched to said firstplurality of transistors; second means operable by a second part of saiddigital input signal for developing in said output line a flow ofcurrent representing the summation of the currents of any of said secondplurality of transistors selected in accordance with said second part ofsaid digital input signal; said second means including means toattenuate the current contribution from said second transistor asdeveloped in said output line to provide for proper relative weightingbetween that current contribution and the contribution of said firsttransistors; circuit means for said second transistors to set differentlevels of current therethrough according to said predetermined weightingpattern, the sum of the currents produced in said output line by saidsecond transistors, after attenuation by said attenuation means,representing an additive supplement to the analog output signal inaccordance with said second part of said digital input signal, properlyweighted relative to said contribution of said first transistors; eachof said second transistors being formed to present a respectiveconductive area proportional to the particular current level assignedthereto in accordance with said predetermined weighting pattern toprovide a current density in said second transistors which is uniformand equal to the current density of said first transistors.Baddend...Badd.12. A converter as in claim 11, wherein all of said transistorsinclude base, emitter and collector electrodes;the area of each of saidtransistor emitters being proportional to the magnitude of currenttherethrough. .Baddend. .Badd.13. A converter as in claim 12, whereinsaid second transistors are formed on a second substrate different fromthe substrate carrying said first transistors. .Baddend. .Badd.14. Aconverter as in claim 12, wherein said first transistors are four innumber and carry respective currents in the ratio of 8:4:2:1; saidsecond transistors being four in number and arranged to carry respectivecurrents in the ratio of 8:4:2:1. .Baddend. .Badd.15. A converter as inclaim 1, including a second plurality of integrated-circuit transistorsat least substantially identical to said first plurality of transistorsand operable to produce a second summation current corresponding to asecond, lower-order part of said digital input; and attenuation meanscoupling said second summation current to said summing means to augmentthe summation current from said first plurality of transistors by thecurrent from said second plurality of transistors attenuated by a factorcorresponding to the relationship between said lower-order digitalsignal part and the order of the digital signal controlling said firstplurality of transistors. .Baddend.